An on-line test strategy and analysis for a 1T1R crossbar memory

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dc.contributor.authorEscudero-Lopez, M.
dc.contributor.authorMoll, F.
dc.contributor.authorRubio, A.
dc.contributor.authorVourkas, Ioannis
dc.date.accessioned2022-05-16T20:30:51Z
dc.date.available2022-05-16T20:30:51Z
dc.date.issued2017
dc.description.abstractMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array.
dc.fuente.origenIEEE
dc.identifier.doi10.1109/IOLTS.2017.8046206
dc.identifier.eisbn9781538603529
dc.identifier.isbn9781538603536
dc.identifier.issn1942-9401
dc.identifier.urihttps://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8046206
dc.identifier.urihttps://doi.org/10.1109/IOLTS.2017.8046206
dc.identifier.urihttps://repositorio.uc.cl/handle/11534/64010
dc.information.autorucEscuela de ingeniería ; Ioannis, Vourkas ; S/I ; 1024131
dc.language.isoen
dc.nota.accesoContenido parcial
dc.pagina.final125
dc.pagina.inicio120
dc.publisherIEEE
dc.relation.ispartofIEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) (23° : 2017 : Thessaloniki, Grecia)
dc.rightsacceso restringido
dc.subjectMemristors
dc.subjectCircuit faults
dc.subjectMicroprocessors
dc.subjectComputer architecture
dc.subjectResistance
dc.subjectTransistors
dc.subjectInverters
dc.titleAn on-line test strategy and analysis for a 1T1R crossbar memoryes_ES
dc.typecomunicación de congreso
sipa.codpersvinculados1024131
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